Image processing system and image processing apparatus for configuring logical circuit on circuit according to configuration data

ABSTRACT

An image processing system includes, a reconfigurable circuit, a storage unit storing first configuration data for a first logical circuit in a predetermined area on the reconfigurable circuit, and second configuration data for a second logical circuit in the predetermined area, and a configuration unit configured to perform first configuration processing for configuring the first logical circuit in the predetermined area, by using the stored first configuration data and predetermined configuration data, on the predetermined area and a different area, and to perform second configuration processing for configuring the second logical circuit in the predetermined area, by using the stored second configuration data and predetermined configuration data, on the predetermined area and the different area. The predetermined configuration data used for the first configuration processing and the predetermined configuration data used for the second configuration processing are not stored in a duplicated way.

BACKGROUND OF THE INVENTION

1. Field of the Invention

One disclosed aspect of the embodiments relates to an image processingapparatus for handling image data, a method for controlling the imageprocessing apparatus, and a program therefor.

2. Description of the Related Art

Programmable logic devices (PLDs) such as complex programmable logicdevices (CPLDs) and field programmable gate arrays (FPGAs) havinginternal programmable logical circuits are well known. In a PLD, logicalcircuit configuration information (hereinafter referred to asconfiguration data) stored in a read only memory (ROM) for configurationis written in a configuration memory which is an internal volatilememory. With this write operation, the operation of each logical blockin the PLD is changed to configure a logical circuit. Writingconfiguration data in a PLD is referred to as configuration.

Recent PLDs are capable of performing partial reconfiguration of logicalcircuits. More specifically, changing the contents of the configurationdata of a certain portion on the configuration memory enables changingonly the operation of a logical block included in an area correspondingto the relevant certain portion out of all areas having a plurality oflogical blocks included in the PLD. Japanese Patent ApplicationLaid-Open No. 2011-186981 discusses a method for sequentiallyconfiguring a plurality of logical circuits configuring a pipeline indifferent areas in a PLD according to the progress of pipelineprocessing by using a partial reconfiguration technique.

The configuration data is stored in the ROM for configuration. Whenimplementing a plurality of types of logical circuits, a plurality oftypes of configuration data is stored in this ROM, and differencesbetween the plurality of types of configuration data stored in the ROMmay be small.

In other words, since an identical portion of the configuration data isstored in the ROM in a duplicated way, the memory capacity required forstoring the configuration data had increased.

SUMMARY OF THE INVENTION

According to an aspect of the disclosure, an image processing systemincludes a reconfigurable circuit capable of configuring a logicalcircuit according to configuration data, a storage unit configured tostore first configuration data for configuring a first logical circuitin a predetermined area on the circuit, and second configuration datafor configuring a second logical circuit in the predetermined area, anda configuration unit configured to perform first configurationprocessing for configuring the first logical circuit in thepredetermined area, by using the stored first configuration data andpredetermined configuration data, on the predetermined area and an areadifferent from the predetermined area, and to perform secondconfiguration processing for configuring the second logical circuit inthe predetermined area, by using the stored second configuration dataand predetermined configuration data, on the predetermined area and thedifferent area. A logical circuit configured in the different area bythe first configuration processing and a logical circuit configured inthe different area by the second configuration processing are identical.The predetermined configuration data used for the first configurationprocessing and the predetermined configuration data used for the secondconfiguration processing are not stored in the storage unit in aduplicated way.

Further features of the disclosure will become apparent from thefollowing description of exemplary embodiments with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an example of a configuration ofan image processing apparatus according to a first exemplary embodiment.

FIG. 2 is a block diagram illustrating a configuration related todynamic partial reconfiguration in the image processing apparatusaccording to the first exemplary embodiment.

FIG. 3 illustrates an example of a conventional method for storingconfiguration data.

FIGS. 4A and 4B illustrate in detail a configuration data structure forreconfiguring a partial reconfiguration portion in the image processingapparatus according to the first exemplary embodiment.

FIG. 5 illustrates an example of a method for storing configuration datain the image processing apparatus according to the first exemplaryembodiment.

FIG. 6 is a flowchart illustrating job execution processing control inthe image processing apparatus according to the first exemplaryembodiment.

FIG. 7 is a flowchart illustrating in detail a processing flow ofdynamic partial reconfiguration in the image processing apparatusaccording to the first exemplary embodiment.

FIG. 8 is a flowchart illustrating in detail a processing flow ofdynamic partial reconfiguration in an image processing apparatusaccording to a second exemplary embodiment.

DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the disclosure will be described below.

[Configuration of Image Processing Apparatus]

A first exemplary embodiment will be described below. FIG. 1 is a blockdiagram illustrating a hardware configuration of an image processingapparatus (image processing system) according to the present exemplaryembodiment. An image processing apparatus 100 according to the presentexemplary embodiment includes an operation unit 103 for enabling a userof the image processing apparatus 100 to perform various operations, ascanner unit 109 for reading image information according to aninstruction from the operation unit 103, and a printer unit 107 forprinting image data on paper. A scanner unit 109 includes a centralprocessing unit (CPU) (not illustrated) for controlling the scanner unit109, and an illumination lamp, a scanning mirror, etc. (not illustrated)for reading a document. The printer unit 107 includes a CPU (notillustrated) for controlling the printer unit 107, and photosensitivedrums and a fixing unit (not illustrated) for performing image formingand fixing, respectively.

The image processing apparatus 100 includes a CPU 101 for totallycontrolling operations of the image processing apparatus 100 byexecuting control software for controlling each unit of image processingapparatus 100. The image processing apparatus 100 further includes aread only memory (ROM) 104 storing programs to be executed by the CPU101. The image processing apparatus 100 further includes a random accessmemory (RAM) 111 which serves as a system work memory used by the CPU101 to operate and also as an image memory for temporarily storing imagedata. The image processing apparatus 100 further includes a memorycontroller 110 for controlling write and read operations for the RAM111. The memory controller 110 is connected to a system bus 120 and animage bus 121, and controls access to the RAM 111.

The image processing apparatus 100 further includes an FPGA 140 as aprogrammable logic device having a reconfigurable circuit capable ofconfiguring a logical circuit. Although, in the present exemplaryembodiment, the FPGA 140 will be described below as a programmable logicdevice, a device having a circuit capable of configuring a logicalcircuit may be used as a programmable logic device. The FPGA 140according to the present exemplary embodiment is a device capable ofperforming partial reconfiguration.

The image processing apparatus 100 further includes a configurationcontroller 130 and a ROM for configuration 150. The configurationcontroller 130 acquires configuration data from the ROM forconfiguration 150 and writes the configuration data in the configurationmemory of the FPGA 140, under control of the CPU 101. The FPGA 140configures a logical circuit by setting operations of an internallogical block according to the written configuration data. Configuring alogical circuit by writing configuration data is referred to asconfiguration. More specifically, the FPGA 140 includes a circuitcapable of configuring a logical circuit according to the configurationdata.

The image processing apparatus 100 further includes a scanner interface(I/F) 108 for inputting image data from the scanner unit 109, and aprinter I/F 106 for outputting image data to the printer unit 107. TheFPGA 140, the scanner I/F 108, and the printer I/F 106 are connected tothe image bus 121 for transmitting image data to be processed.

The image processing apparatus 100 communicates with (transmits andreceives data to/from) a general-purpose computer (not illustrated) on anetwork via a network I/F 102. The image processing apparatus 100further communicates with (transmits and receives data to/from) ageneral purpose computer (not illustrated) connected with the imageprocessing apparatus 100 via a universal serial bus (USB) I/F 114. Theimage processing apparatus 100 connects with a public line network andfurther communicates with (transmits and receives data to/from) otherimage processing apparatus and a facsimile machine (not illustrated),via a FAX (facsimile) I/F 115. The image processing apparatus 100includes a ROM I/F 112 for controlling programs to be executed by theCPU 101, and read and write operations on the ROM 104. The imageprocessing apparatus 100 further includes the system bus 120 formutually connecting the CPU 101, the network I/F 102, the operation unit103, the ROM I/F 112, the configuration controller 130, and the FPGA140. The CPU 101 performs parameter setting on logical circuits of theFPGA 140 and parameter setting on the scanner I/F 108 and the printerI/F 106, via the system bus 120.

[Configuration for Partial Reconfiguration]

Partial reconfiguration in the image processing apparatus 100 accordingto the present exemplary embodiment will be described below withreference to FIG. 2. FIG. 2 is a block diagram illustrating aconfiguration for partial reconfiguration in the image processingapparatus 100.

The CPU 101, the configuration controller 130, the ROM for configuration150, and the FPGA 140 are as described above with reference to FIG. 1.

The FPGA 140 includes an area having a plurality of logical blocks. Inthe FPGA 140 capable of performing partial reconfiguration, this areacan be divided into a plurality of portions, and a logical circuit canbe individually changed for each division portion. Referring to FIG. 2,the respective division portions are referred to as a partialreconfiguration portion 201 and a fixed portion 202. When performingpartial reconfiguration on a logical circuit in the partialreconfiguration portion 201, the operation of a logical block includedin the fixed portion 202 remains unchanged (fixed). The partialreconfiguration portion 201 and the fixed portion 202 are arranged onthe same column. This means that, when performing partialreconfiguration on a logical circuit in the partial reconfigurationportion 201, writing is performed not only on the partialreconfiguration portion 201 but also on the configuration memorycorresponding to the fixed portion 202, as described below.

The configuration controller 130 has a function of managing partialreconfiguration for each partial reconfiguration portion 201. Forexample, upon reception of an instruction for executing configuration onthe partial reconfiguration portion 201 from the CPU 101, theconfiguration controller 130 reads the configuration data for changingthe logical circuit of the partial reconfiguration portion 201 from theROM for configuration 150. Then, the configuration controller 130transmits the read configuration data to the FPGA 140. The FPGA 140writes the transmitted configuration data in the corresponding portionof the configuration memory to configure a logical circuit in thepartial reconfiguration portion 201. Configuration procedures will bedescribed in detail below with reference to FIGS. 4A to 7.

A conventional method for storing the configuration data of a logicalcircuit configured in the partial reconfiguration portion 201 of theFPGA 140 will be described below with reference to FIG. 3.

FIG. 3 illustrates an example of configuration data corresponding to thepartial reconfiguration portion 201 of the FPGA 140 stored in the ROMfor configuration 150. In this example, the partial reconfigurationportion 201 stores the configuration data 300 for the partialreconfiguration portion 201 (the configuration data for function A 301to the configuration data for function D 304) for configuring logicalcircuits for functions A to D.

Storing the configuration data 300 for partial reconfiguration portion201 in the ROM for configuration 150 for each function in this wayenables configuring logical circuits having various functions in thepartial reconfiguration portion 201. However, with the increase in thenumber of functions, the total amount of configuration data stored inthe ROM for configuration 150 increases.

<Descriptions of Configuration of Configuration Data for PartialReconfiguration>

Configuration based on configuration data for a specific function (forexample, the above-described function A) will be described below withreference to FIGS. 4A and 4B and subsequent drawings.

An example design of the partial reconfiguration portion of the FPGA 140will be described below with reference to FIG. 4A. FIG. 4A is aconceptual view illustrating the configuration memory in the FPGA 140according to the present exemplary embodiment. Generally, whenperforming partial reconfiguration on the FPGA, a designer determineswhich portion of the configuration memory inside the FPGA corresponds tothe partial reconfiguration portion. “A certain portion of theconfiguration memory corresponds to the partial reconfiguration portion”means a relation that rewriting configuration data written in therelevant portion changes the operation of the logical block included inthe relevant partial reconfiguration portion. More specifically, onlythe logical circuit of the partial reconfiguration portion is changed.In the example illustrated in FIG. 4A, the portion of the configurationmemory rewritten to change the operation of the logical block includedin the partial reconfiguration portion 201 is referred to as a memoryfor partial reconfiguration portion 401. On the other hand, a memory forfixed portion 402 illustrated in FIG. 4A refers to a portion of theconfiguration memory which is rewritten when changing the operation ofthe logical block included in the fixed portion 202.

The following descriptions assume performing partial reconfiguration ofa desired logical circuit in the partial reconfiguration portion 201.More specifically, the contents of the logical circuit configured in thefixed portion 202 remain unchanged.

<Procedures of Configuration Processing>

Procedures for configuration processing in partial reconfiguration willbe described below. In the FPGA, configuration data is written in theconfiguration memory not in free units but in minimum writing units. Forexample, schematically speaking, some FPGA devices have a minimumrewriting unit of one column prolonging from the top to the bottom ofthe configuration memory, and other FPGA devices have a minimumrewriting unit of one row or a square area having a specific size. Morespecifically, when partially configuring a logical circuit in thepartial reconfiguration portion 201, it may be necessary to writeconfiguration data not only in the memory for partial reconfigurationportion 401 but also in the memory for fixed portion 402.

For example, the configuration memory of the FPGA 140 according to thepresent exemplary embodiment has a minimum writing unit of one column.Therefore, when configuring a logical circuit in the partialreconfiguration portion 201, the memory for fixed portion 402 located onthe same column as the memory for partial reconfiguration portion 401 isalso subjected to configuration data writing (a configuration datawriting target). Therefore, such configuration data for the memory forfixed portion 402 that does not change the contents of the logicalcircuit configured in the fixed portion 202 is required.

Conventionally, configuration data that does not change the contents ofthe logical circuit of the fixed portion 202 and configuration data fora logical circuit having a function to be configured in the partialreconfiguration portion 201 are collectively used as the configurationdata 300 for the partial reconfiguration portion 201. More specifically,the configuration data for function A 301 includes configuration datathat does not change the contents of the logical circuit of the fixedportion 202, and configuration data of a logical circuit having thefunction A to be configured in the partial reconfiguration portion 201.This also applies to configuration data 302 to 304 for functions B to D.Therefore, in the configuration data 300 for the partial reconfigurationportion 201 (refer to FIG. 3), some data contents in the configurationdata for function A 301 to the configuration data for function D 304 areduplicated. For example, “configuration data that does not change thecontents of the logical circuit of the fixed portion 202” is duplicated.More specifically, when there is a plurality of functions A to D, theROM for configuration 150 conventionally stores configuration datahaving completely the same contents in a duplicated way. This is one ofcauses of the decrease in the capacity of the ROM for configuration 150.

<Detailed Procedures of Configuration Processing>

Configuration for configuring a logical circuit (a specific logicalcircuit) having a specific function in the partial reconfigurationportion 201 will be described in detail below with reference to FIG. 4B.The minimum writing unit of the configuration memory for performingpartial reconfiguration is a column.

Configuration data for partial reconfiguration 410 illustrated in FIG.4B is, for example, the configuration data for function A 301 in theconfiguration data 300 for the partial reconfiguration portion 201illustrated in FIG. 3. The configuration data for partialreconfiguration 410 includes configuration data for logical AND 411 andconfiguration data for logical OR 414. Configuration refer to acquiringthe following processing results (1) and (2). (1) Firstly, configurationdata currently written in the memory for partial reconfiguration portion401 is cleared to “0.” (2) Secondly, configuration data for configuringa specific logical circuit is written in the memory for partialreconfiguration portion 401. However, note that the writing ofconfiguration data at the time of configuration is performed only incolumn units.

More specifically, the configuration controller 130 transmits to theFPGA 140 the configuration data for logical AND 411 for clearing theconfiguration data currently written in the memory for partialreconfiguration portion 401 to “0.” In this case, the configurationcontroller 130 transmits the configuration data for logical AND 411illustrated in FIG. 4B in order of data to be written in the firstcolumn, data to be written in the second column, and so on in theconfiguration memory. More specifically, the configuration data istransmitted in column units. In more detail, data to be written in onecolumn is transmitted in order from the top downward in the column.Therefore, in the example illustrated in FIG. 4B, configuration data forpartial reconfiguration portion logical AND 412 and configuration datafor fixed portion logical AND 413 are alternately transmitted. Thistransmission includes an instruction for updating the configuration datacurrently written in the memory for partial reconfiguration portion 401and the memory for fixed portion 402 in the FPGA 140 with the results ofthe respective logical AND operations with the configuration data forlogical AND 411.

The configuration data for logical AND 411 includes the configurationdata for partial reconfiguration portion logical AND 412 and theconfiguration data for fixed portion logical AND 413. The configurationdata for partial reconfiguration portion logical AND 412 consists of bitstream data of all “0s.” The configuration data for fixed portionlogical AND 413 consists of bit stream data of all “1s”. Therefore,although updating is performed in column units of the configurationmemory, the writing on the configuration data for fixed portion logicalAND 413 is performed without changing the contents of the configurationdata currently written in the memory for fixed portion 402.

Then, the configuration controller 130 transmits to the FPGA 140 theconfiguration data for logical OR 414 for configuring a logical circuitfor the function A in the memory for partial reconfiguration portion401. In this case, the configuration controller 130 transmits theconfiguration data for logical OR 414 illustrated in FIG. 4B in order ofdata to be written in the first column, data to be written in the secondcolumn, and so on in the configuration memory. More specifically, alsoin this case, configuration data is transmitted in column units. Asdescribed above, data to be written in one column is also transmitted inorder from the top downward in the column. Therefore, in the exampleillustrated in FIG. 4B, configuration data for partial reconfigurationportion function 415 and configuration data for fixed portion logical OR416 are alternately transmitted. This transmission includes aninstruction for updating the configuration data currently written in thememory for partial reconfiguration portion 401 and the memory for fixedportion 402 in the FPGA 140, which has already been updated throughlogical AND, with the results of the respective logical OR operationswith the configuration data for logical OR 414.

The configuration data for logical OR 414 includes the configurationdata for partial reconfiguration portion function 415 and theconfiguration data for fixed portion logical OR 416. The configurationdata for partial reconfiguration portion function 415 consists of bitstream data corresponding to the logical circuit of a specific function(for example, the function A). The configuration data for fixed portionlogical OR 416 consist of bit stream data of all “0s.” Therefore,although updating is performed in column units of the configurationmemory, the writing on the configuration data for fixed portion logicalOR 416 is performed without changing the contents of the memory forfixed portion 402.

As described above, the configuration controller 130 writes theconfiguration data for partial reconfiguration 410 (for example, theconfiguration data for function A 301) in the memory for partialreconfiguration portion 401 and the memory for fixed portion 402 incolumn units.

A point which should be noted here is that bit stream data pieces havingthe same contents are conventionally stored in a duplicated manner inthe ROM for configuration 150 as separate configuration data pieces forconfiguring logical circuits having different functions in the partialreconfiguration portion 201. More specifically, the configuration datafor logical AND 411 and the configuration data for fixed portion logicalOR 416 having the same contents are duplicated between differentconfiguration data pieces. The following describes a method for storingconfiguration data commonly usable while avoiding wasteful duplication.Although the present exemplary embodiment is on the premise that theminimum writing unit of an FPGA device is a column, the disclosure isnot limited thereto. More specifically, configuration data for commonuse is stored in different ways according to the minimum writing unit ofan FPGA device differs.

<Configuration Data Stored in ROM for Configuration>

Configuration data to be stored in the ROM for configuration 150according to the present exemplary embodiment will be described belowwith reference to FIG. 5.

FIG. 5 illustrates the configuration data to be stored in the ROM forconfiguration 150 according to the present exemplary embodiment. The ROMfor configuration 150 according to the present exemplary embodimentincludes configuration data for common portion 501, configuration datafor function A 502, configuration data for function B 503, configurationdata for function C 504, and configuration data for function D 505. Theconfiguration data for common portion 501 corresponds to theconfiguration data for logical AND 411 and the configuration data forfixed portion logical OR 416 illustrated in FIG. 4B. The configurationdata for function A 502 to the configuration data for function D 505correspond to the configuration data for partial reconfiguration portionfunction 415 illustrated in FIG. 4B.

The present exemplary embodiment is characterized in that theconfiguration data for common portion 501 is used in combination withthe configuration data for function A 502 to the configuration data forfunction D 505. When configuring a logical circuit for each function inthe partial reconfiguration portion 201, the configuration data forcommon portion 501 is repetitively used for column-based configurationprocessing for each function. Thus, providing the configuration data forcommon portion 501 enables avoiding data duplication in theconfiguration data for function A 502 to the configuration data forfunction D 505, thus reducing the total amount of configuration datacompared with the conventional method.

Each piece of configuration data will be described in detail below.

The configuration data for common portion 501 is stored, for example, inaddresses Ox0000 to Ox1FFF in the ROM for configuration 150. Theconfiguration data for common portion 501 includes the configurationdata for logical AND 411 and the configuration data for fixed portionlogical OR 416 illustrated in FIG. 4B. The configuration data forlogical AND 411 is stored in addresses 0x0000 to 0x0FFF. Theconfiguration data for fixed portion logical OR 416 is stored inaddresses 0x1000 to 0x1FFF. In the present exemplary embodiment, boththe configuration data for logical AND 411 and the configuration datafor fixed portion logical OR 416 are arranged and stored in order ofcolumns of the writing target configuration memory. For example, bitstream data corresponding to the first column is stored, for example, inaddresses 0x0000 to 0x007F, and bit stream data corresponding to thesecond column is stored, for example, in addresses 0x0080 to 0x00FF. Howthe configuration data for common portion 501 is used for theconfiguration memory will be described below.

The configuration data for function A 502 is bit stream datacorresponding to the logical circuit for function A which is stored, forexample, in addresses 0x2000 to 0x2FFF in the ROM for configuration 150.The configuration data for function A 502 corresponds to theconfiguration data for partial reconfiguration portion function 415illustrated in FIG. 4B. The bit stream data corresponding to the logicalcircuit for function A is also arranged and stored in order of columnsof the writing target configuration memory.

Similarly, the configuration data for function B 503, the configurationdata for function C 504, and the configuration data for function D 505are also stored in the ROM for configuration 150. The configuration data503, 504, and 505 also correspond to the configuration data for partialreconfiguration portion function 415 illustrated in FIG. 4B.

<Configuration Processing Flow>

FIG. 6 is a flowchart illustrating job execution processing control ofthe image processing apparatus according to the present exemplaryembodiment. Each step in the flowchart illustrated in FIG. 6 isimplemented when the CPU 101 executes a program stored in the ROM 104.More specifically, the CPU 101 under program execution controls theconfiguration controller 103. In the following processing, a logicalcircuit is considered to be configured in the partial reconfigurationportion 201.

In step S601, the CPU 101 waits for a job to be executed. Morespecifically, the CPU 101 determines whether a job has been received.When a job has been received (YES in step S601), the processing proceedsto step S602.

In step S602, when executing the job received in step S601, the CPU 101identifies a logical circuit (function) to be configured in the partialreconfiguration portion 201 of the FPGA 140 according to the processingcontents of the received job. For example, when the processing contentsof the received job requires the function A, the CPU 101 identifies alogical circuit for function A as a logical circuit to be configured inthe configuration memory. In this case, for example, a logical circuithaving another function is configured in the fixed portion 202, and dataprocessing is being executed.

In step S603, the CPU 101 controls the configuration controller 130 toconfigure the logical circuit identified in step S602 in the partialreconfiguration portion 201. This processing will be described in detailbelow with reference to FIG. 7.

In step S604, the CPU 101 determines whether the configurationprocessing is completed. This determination will be described in detailbelow. The configuration controller 130 receives an end signalindicating the completion of the configuration processing from the FPGA140. Then, the configuration controller 130 notifies the CPU 101 of thereception of the end signal. Upon reception of the notification, the CPU101 determines that the configuration processing is completed. When theCPU 101 determines that the configuration processing is completed (YESin step S604), the processing proceeds to step S605. On the other hand,when the CPU 101 determines that the configuration processing is notcompleted (NO in step S604), the processing waits in step S604 (untilthe configuration controller 130 receives the configuration end signalfrom the FPGA 140).

In step S605, the CPU 101 performs data processing of the received jobby using the logical circuit configured on the configuration memorythrough the configuration processing in step S603.

This completes descriptions of procedures for executing the receivedjob.

A flowchart illustrating in detail the configuration processingperformed in step S603 will be described below with reference to FIG. 7.Each step in the flowchart illustrated in FIG. 7 is performed by the CPU101 and the configuration controller 130 under control of the CPU 101.In this case, a logical circuit will be configured in the partialreconfiguration portion 201.

In step S701, the CPU 101 instructs the configuration controller 130 toperform the following processing (1) and (2).

Processing (1): The configuration controller 130 reads and acquires theconfiguration data for logical AND 411 stored in addresses 0x0000 to0x0FFF in the ROM for configuration 150 illustrated in FIG. 5.

Processing (2): The configuration controller 130 transmits the acquiredconfiguration data for logical AND 411 to the FPGA 140 in column units.In this transmission, the configuration controller 130 instructs theFPGA 140 to perform the following processing. The FPGA 140 performs thelogical AND operation between the configuration data for logical AND 411and the configuration data already written in the configuration memoryof the FPGA 140. Then, the FPGA 140 writes the result of the relevantoperation back in the configuration memory.

As described above with reference to FIG. 4B, the FPGA 140 writes datain column units in the memory for partial reconfiguration portion 401and the memory for fixed portion 402 by using the configuration data forlogical AND 411.

The processing in step S701 is not limited thereto. For example, theconfiguration controller 130 may reads the configuration data (bitstream data) from address 0x0000 in the ROM for configuration 150, andsequentially transmit the configuration data to the FPGA 140.

In step S702, the CPU 101 instructs the configuration controller 130 toperform the following processing (1), (2), and (3).

Processing (1): The configuration controller 130 reads from the ROM forconfiguration 150 the configuration data (the configuration data forpartial reconfiguration portion function 415) used to configure thelogical circuit identified in step S602. For example, in the case of thelogical circuit for function A, the configuration controller 130 readsthe configuration data for function A from addresses 0x2000 to 0x2FFF inthe ROM for configuration 150.

Processing (2): The configuration controller 130 reads and acquires theconfiguration data for fixed portion logical OR 416 stored in addresses0x1000 to 0x1FFF in the ROM for configuration 150 illustrated in FIG. 5.

Processing (3): The configuration controller 130 merges two differentpieces of the read configuration data. This merging is intended toenable writing the configuration data as a result of merging in theconfiguration memory in column units, i.e., processing for rearrangingthe bit stream data configuring two different pieces of theconfiguration data. Further, this merging is performed according to theposition in the memory for partial reconfiguration portion 401 in theconfiguration memory. More specifically, the configuration data acquiredby the merging is bit stream data for changing the contents of theconfiguration data currently written in the memory for partialreconfiguration portion 401.

For example, referring to FIG. 4B, bit stream data “100” in the firstcolumn of the configuration data for partial reconfiguration portionfunction 415 is merged with bit stream data “000000” in the first columnof the configuration data for fixed portion logical OR 416. Since theposition of the memory for partial reconfiguration portion 401 is in theupper portion of the column, the bit stream data “100” is arranged inthe upper portion of the column and the bit stream data “000000” isarranged in the following portion as a result of this merging. After themerging, bit stream data “100000000” corresponds to the first column.

If the position of the memory for partial reconfiguration portion 401 isin the middle portion of the column, the bit stream data “000000” in thefirst column of the configuration data for fixed portion logical OR 416is divided into the upper and lower halves of the column, and the bitstream data “100” is arranged in the middle portion. This means that,after the merging, the bit stream data becomes “000100000.”

This also applies to the second column. More specifically, bit streamdata “111” in the second column of the configuration data for partialreconfiguration portion function 415 is merged with bit stream data“000000” in the second column of the configuration data for fixedportion logical OR 416. Then, bit stream data “111000000” after themerging corresponding to the second column is rearranged after the bitstream data “100000000” after the merging, corresponding to the firstcolumn, already acquired. More specifically, bit stream data“100000000111000000” is acquired.

The above-described merge processing may be performed by using a memory(not illustrated) in the configuration controller 130 or by using theRAM 111.

In step S703, the CPU 101 instructs the configuration controller 130 toperform the following processing. The configuration controller 130transmits to the FPGA 140 the configuration data (for example,“100000000111000000 . . . ”) acquired by the merging in step S702. Inthis transmission, the configuration controller 130 instructs the FPGA140 to perform the following processing. The FPGA 140 performs thelogical OR operation between the configuration data acquired by themerging and the configuration data written in the configuration memoryafter the processing in step S701. Then, the FPGA 140 writes the resultof the relevant operation back in the configuration memory. As describedwith reference to FIG. 4B, the FPGA 140 writes data in column units inthe memory for partial reconfiguration portion 401 and the memory forfixed portion 402 by using the configuration data for partialreconfiguration portion function 415 and the configuration data forfixed portion logical OR 416.

Upon completion of the processing in step S703, the processing proceedsto step S604 illustrated in FIG. 6. The configuration processing isperformed in this way. More specifically, the logical circuit configuredin the fixed portion 202 after the configuration processing is identicalregardless of the logical circuit (for example, the logical circuit forfunction A, the logical circuit for function B, etc.) configured in thepartial reconfiguration portion 201.

In steps S702 and S703, the CPU 101 may operate as follows. The CPU 101instructs the configuration controller 130 to acquire two differentpieces of configuration data and transmit the relevant configurationdata to the CPU 101. Then, the CPU 101 merges two different pieces ofthe transmitted configuration data into data in column units, asdescribed above. Then, the CPU 101 instructs the configurationcontroller 130 to write the relevant data after the merging in the FPGA140.

In steps S702 and S703, alternatively, the CPU 101 may instruct theconfiguration controller 130 to perform the following processing. Theconfiguration controller 130 performs the following processing to writethe configuration data in column units. The configuration controller 130performs processing for alternately reading a part of the configurationdata for functions A to D and a part of the configuration data for fixedportion logical OR 416 from the ROM for configuration 150. Then, theconfiguration controller 130 sequentially transmits the configurationdata to the FPGA 140 in order of reading.

This sequential transmission will be described below with reference toFIG. 4B. (1′) Firstly, the configuration controller 130 reads data “100”corresponding to the first column of the configuration data for partialreconfiguration portion function 415, from the ROM for configuration150, and transmits the data to the FPGA 150. (2′) Secondly, theconfiguration controller 130 reads data “000000” corresponding to thefirst column of the configuration data for fixed portion logical OR 416,from the ROM for configuration 150, and transmits the data to the FPGA150. (3′) The configuration controller 130 reads data “111”corresponding to the second column of the configuration data for partialreconfiguration portion function 415, from the ROM for configuration150, and transmits the data to the FPGA 150. (4′) The configurationcontroller 130 reads data “000000” corresponding to the second column ofthe configuration data for fixed portion logical OR 416, from the ROMfor configuration 150, and transmits the data to the FPGA 150. Theabove-described reading and transmission are alternately repeated foreach column.

Performing merge control on the configuration data described withreference to FIG. 7 enables repetitively using common configuration datawhen configuring logical circuits having a plurality of functions. Inthis case, only one piece of common configuration data which isrepetitively usable needs to be stored in the ROM for configuration 150.Accordingly, the total amount of configuration data to be stored can bereduced, of course, without degrading the flexible writing performanceof the logical circuit.

A second exemplary embodiment will be described below. In theabove-described first exemplary embodiment, the configuration data forcommon portion 501 is stored in the ROM for configuration 150. In thepresent exemplary embodiment, when performing configuration processing,the configuration data for common portion 501 is dynamically generatedwithout storing the configuration data for common portion 501 in the ROMfor configuration 150.

The image processing apparatus (image processing system) 100 accordingto the present exemplary embodiment is almost similar to the imageprocessing apparatus 100 according to the first exemplary embodimentillustrated in FIGS. 1 and 2. The present exemplary embodiment differsfrom the first exemplary embodiment in that the configuration data forcommon portion 501 is not stored in the ROM for configuration 150 andthat the configuration controller 130 generates the configuration datafor partial reconfiguration. More specifically, the configurationcontroller 130 generates bit stream data corresponding to theconfiguration data for logical AND 411 and the configuration data forlogical OR 414 illustrated in FIG. 4B.

A processing flow performed by the image processing apparatus 100according to the present exemplary embodiment is similar to thatillustrated in FIG. 6. The processing flow according to the presentexemplary embodiment differs from the processing flow according to thefirst exemplary embodiment in that the processing performed in step S603is processing in the flowchart illustrated in FIG. 8.

The processing in the flowchart illustrated in FIG. 8 is implementedwhen the CPU 101 executes a program stored in the ROM 104 to control theconfiguration controller 130. For convenience of descriptions, thefollowing descriptions will be made based on the partial reconfigurationtarget areas and the configuration data for partial reconfigurationillustrated in FIGS. 4A and 4B, respectively.

In step S801, the CPU 101 instructs the configuration controller 130 toperform the following processing. The configuration controller 130generates the configuration data for logical AND 411 illustrated in FIG.4B in order of columns of the configuration memory. The configurationdata generation in order of columns is performed as follows. (1)Firstly, the configuration controller 130 references the position of thepartial reconfiguration target area in the configuration memory. Forexample, referring to FIG. 4A, the configuration controller 130 confirmsthat the position of the memory for partial reconfiguration portion 401is the upper left position of the configuration memory. (2) Secondly,the configuration controller 130 generates bit stream data in columnunits so that data “0” is to be written at the referenced position inthe configuration memory. For example, referring to FIG. 4B, theconfiguration controller 130 generates bit stream data “000111111” forthe first column of the configuration memory. Then, the configurationcontroller 130 generates bit stream data “000111111” for the secondcolumn. This also applies to the subsequent columns. Bit stream datacorresponding to all columns related to the partial configuration targetarea corresponds to the configuration data for logical AND 411illustrated in FIG. 4B.

In step S802, the CPU 101 instructs the configuration controller 130 toperform the following processing. The configuration controller 130performs the processing (for transmitting the generated configurationdata for logical AND 411) described in the processing (2) in step S701illustrated in FIG. 7.

In step S803, the CPU 101 instructs the configuration controller 130 toperform the following processing. The configuration controller 130performs the processing (for reading the configuration data for partialreconfiguration portion function 415) described in the processing (1) instep S702 illustrated in FIG. 7.

In step S804, the CPU 101 instructs the configuration controller 130 toperform the following processing. The configuration controller 130generates the configuration data for fixed portion logical OR 416illustrated in FIG. 4B in order of columns of the configuration memory.This configuration data in order of columns is bit-stream data having“0” as all elements.

In step S805, the CPU 101 instructs the configuration controller 130 toperform the following processing. The configuration controller 130merges the configuration data for partial reconfiguration portionfunction 415 read in step S803 and the configuration data for fixedportion logical OR 416 generated in step S804. This merging is similarto the processing (for merging two different pieces of configurationdata) described in the processing (3) in step S702 illustrated in FIG.7. More specifically, as described in the processing (3), this mergingacquires such configuration data (bit stream data) in order of columnsthat changes the contents of the configuration data written in thememory for partial reconfiguration portion 401.

In step S806, the CPU 101 instructs the configuration controller 130 toperform the following processing. The configuration controller 130performs processing (for transmitting the configuration data acquired bythe merging) described in the processing in step S703 illustrated inFIG. 7.

Performing the above-described configuration processing enables savingthe memory capacity for the configuration data for common portion 501which should be stored in the ROM for configuration 150.

Other Exemplary Embodiments

In the above-described exemplary embodiments, the FPGA 140 includes onepartial reconfiguration portion, and four different functions A to D areconfigured in the partial reconfiguration portion. However, the numberof partial reconfiguration portions and the number of functions to beconfigured therein are limited only to make descriptions easy tounderstand. The number of partial reconfiguration portions and thenumber of functions to be configured therein are not limited to thenumbers in the above-described exemplary embodiments.

In the above-described exemplary embodiments, since the configurationdata is used in common, the memory capacity for storing theconfiguration data can be reduced.

Other Embodiments

Embodiment(s) of the disclosure can also be realized by a computer of asystem or apparatus that reads out and executes computer executableinstructions (e.g., one or more programs) recorded on a storage medium(which may also be referred to more fully as a ‘non-transitorycomputer-readable storage medium’) to perform the functions of one ormore of the above-described embodiment(s) and/or that includes one ormore circuits (e.g., application specific integrated circuit (ASIC)) forperforming the functions of one or more of the above-describedembodiment(s), and by a method performed by the computer of the systemor apparatus by, for example, reading out and executing the computerexecutable instructions from the storage medium to perform the functionsof one or more of the above-described embodiment(s) and/or controllingthe one or more circuits to perform the functions of one or more of theabove-described embodiment(s). The computer may comprise one or moreprocessors (e.g., central processing unit (CPU), micro processing unit(MPU)) and may include a network of separate computers or separateprocessors to read out and execute the computer executable instructions.The computer executable instructions may be provided to the computer,for example, from a network or the storage medium. The storage mediummay include, for example, one or more of a hard disk, a random-accessmemory (RAM), a read only memory (ROM), a storage of distributedcomputing systems, an optical disk (such as a compact disc (CD), digitalversatile disc (DVD), or Blu-ray Disc (BD)™), a flash memory device, amemory card, and the like.

While the disclosure has been described with reference to exemplaryembodiments, it is to be understood that the disclosure is not limitedto the disclosed exemplary embodiments. The scope of the followingclaims is to be accorded the broadest interpretation so as to encompassall such modifications and equivalent structures and functions.

This application claims the benefit of Japanese Patent Application No.2014-249423, filed Dec. 9, 2014, which is hereby incorporated byreference herein in its entirety.

What is claimed is:
 1. An image processing system comprising: a circuitcapable of configuring a logical circuit according to configurationdata; a storage unit configured to store first configuration data forconfiguring a first logical circuit in a predetermined area on thecircuit, and second configuration data for configuring a second logicalcircuit in the predetermined area; and a configuration unit configuredto perform first configuration processing for configuring the firstlogical circuit in the predetermined area, by using the stored firstconfiguration data and predetermined configuration data, on thepredetermined area and an area different from the predetermined area,and to perform second configuration processing for configuring thesecond logical circuit in the predetermined area, by using the storedsecond configuration data and predetermined configuration data, on thepredetermined area and the different area, wherein a logical circuitconfigured in the different area by the first configuration processingand a logical circuit configured in the different area by the secondconfiguration processing are identical, and wherein the predeterminedconfiguration data used for the first configuration processing and thepredetermined configuration data used for the second configurationprocessing are not stored in the storage unit in a duplicated way. 2.The image processing system according to claim 1, wherein configurationprocessing is processing for writing configuration data in the circuitbased on a predetermined unit.
 3. The image processing system accordingto claim 2, wherein, in the first configuration processing, theconfiguration unit merges the first configuration data and thepredetermined configuration data based on the predetermined unit, andwrites configuration data after the merging in the predetermined areaand the different area based on the predetermined unit.
 4. The imageprocessing system according to claim 3, wherein, in the firstconfiguration processing, the configuration unit performs the mergingbased on the predetermined unit and a position in the predetermined areaon the circuit.
 5. The image processing system according to claim 2,wherein the predetermined unit is one of a column unit, a row unit, anda square area unit.
 6. The image processing system according to claim 2,wherein the predetermined unit is a unit covering the predetermined areaand the different area.
 7. The image processing system according toclaim 1, wherein the configuration unit writes the first configurationdata in the predetermined area, and writes the predeterminedconfiguration data in the different area, thus performing theconfiguration processing for configuring the first logical circuit inthe predetermined area.
 8. The image processing system according toclaim 1, wherein the configuration unit writes the second configurationdata in the predetermined area, and writes the predeterminedconfiguration data in the different area, thus performing theconfiguration processing for configuring the second logical circuit inthe predetermined area.
 9. The image processing system according toclaim 1, wherein the storage unit is configured to store thepredetermined configuration data used for the first configurationprocessing, and wherein the configuration unit performs: acquiring thestored predetermined configuration data from the storage unit in thefirst configuration processing; and acquiring the stored predeterminedconfiguration data from the storage unit in the second configurationprocessing.
 10. The image processing system according to claim 1,wherein the storage unit is configured to store neither thepredetermined configuration data used for the first configurationprocessing nor the predetermined configuration data used for the secondconfiguration processing, and wherein the configuration unit performs:in the first configuration processing, generating the predeterminedconfiguration data used for the first configuration processing; and inthe second configuration processing, generating the predeterminedconfiguration data used for the second configuration processing.
 11. Theimage processing system according to claim 10, wherein the configurationunit generates the predetermined configuration data dependent on aposition in the predetermined area on the circuit.
 12. The imageprocessing system according to claim 1, wherein the predeterminedconfiguration data is used by the configuration unit to perform thefirst and second configuration processing without changing the logicalcircuit configured in the different area.
 13. The image processingsystem according to claim 1, wherein the circuit is a FPGA.
 14. An imageprocessing apparatus comprising: a storage unit configured to storefirst configuration data for configuring a first logical circuit in apredetermined area on a circuit capable of configuring a logical circuitaccording to configuration data, and to store second configuration datafor configuring a second logical circuit in the predetermined area; anda configuration unit configured to perform first configurationprocessing for configuring the first logical circuit in thepredetermined area, by using the stored first configuration data andpredetermined configuration data, on the predetermined area and an areadifferent from the predetermined area, and to perform secondconfiguration processing for configuring the second logical circuit inthe predetermined area, by using the stored second configuration dataand predetermined configuration data, on the predetermined area and thedifferent area, wherein a logical circuit configured in the differentarea by the first configuration processing and a logical circuitconfigured in the different area by the second configuration processingare identical, and wherein the predetermined configuration data used inthe first configuration processing and the predetermined configurationdata used in the second configuration processing are not stored in thestorage unit in a duplicated way.